Most pixel types feature three terminals to drive them:

  1. VCC
  2. 0V
  3. DATA (DI)

However, with advancements in technology, manufacturers have developed chips that require four terminals. An example of tape that uses this technology is ENTTEC’s 8PX60-12-B pixel strip. This is based on the |WorldSemi WS2815 IC with a standard data line plus a backup data line to allow the data to still carry on down the strip if a pixel gets damaged or removed. These four terminals are:

  1. VCC
  2. DATA (DI)
  3. BACKUP DATA (BI)
  4. 0V

In the WS2815 protocol, it is possible to connect just VCC, GND, and DATA to your 3-terminal pixel driver. Better yet, you could splice the data output from the pixel controller to connect to both the Data and Backup Data terminals from your driver.


Another variation of 4 terminal pixels is for clocked protocols (i.e. APA-102). These separate the pixel data and clock data (usually embedded in the single data line). In these pixels, the terminals are as follows:

  1. VCC
  2. DATA (DI)
  3. CLOCK (CLK)
  4. 0V

In this system, the pixel receives data via the data line and then receives information via the clock line, which tells the pixel when to check for data. This helps overcome issues in very long runs of pixel strip, where the pixels might be slightly out of sync from start to end of the run and allows faster refresh rates (2 data lines = twice the bandwidth). If the Clock line is not connected, and if it is not receiving appropriate Clock information, the pixel will not be able to respond to the data it receives.


It is essential to remember that the data line and clock line do not carry the same information. You cannot splice the data line out from a 3-terminal controller to connect to the Data and Clock terminals. The pixels will not respond correctly if this is done. Using a Data + Clock protocol requires a controller that supports clock data.